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@sespivak sespivak commented Jul 31, 2022

This fixes uart test cases according to PR: sigrokproject/libsigrokdecode#91

@sespivak sespivak changed the title uart: bit, data and packet margins refinement uart: bit, data and packet boundaries refinement Aug 1, 2022
@sespivak sespivak force-pushed the uart_fast branch 3 times, most recently from 0df8060 to a782587 Compare August 2, 2022 10:55
@sespivak sespivak marked this pull request as ready for review August 2, 2022 17:41
put expected and actual signal value on parity error
interrupt frame receive on stopbit error
put data packets to python output
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